1. Field of the Invention
The invention relates generally to on-chip testing of electronic integrated circuits and more specifically relates to on-chip test and analysis of clock jitter in a circuit design.
2. Discussion of Related Art
Most digital electronic circuits utilize one or more clock signals to cycle associated digital logic through logic steps in a synchronized manner. A clock signal generally approximates a square waveform and has a fixed clock frequency as required for the particular application. The rising and/or falling edge of the square waveform of each clock period is used to sequence digital logic circuits coupled to the clock signal output to a next state.
It is common in the industry to use Phase Locked Loop (PLL) circuits to generate a clock signal for particular applications in an integrated circuit (IC). The PLL circuit generates a clock signal based on the frequency and phase of applied reference clock signals. In practice, the period of each clock signal pulse may vary within a tolerable time range. Clock jitter is defined as the unwanted variation of a clock period over time. With many present day electronic applications requiring clock frequencies in the hundred's of megahertz to multiple gigahertz range, clock jitter can have a detrimental effect on circuit timing if too excessive. Digital designers attempt to design application circuits to account for an expected range of clock jitter. However, even careful designers may encounter problems in the implementation of their circuit designs if the tight tolerances required for high-speed circuit applications are not met. Therefore, in addition to simulation of circuit designs to test for compliance with required clock signal tolerance, produced circuits (i.e., manufactured or fabricated circuits) are tested to assure compliance with the required clock signal timing tolerance.
Current test methodologies generally require specialized Automated Test Equipment (ATE) to measure clock jitter for production test purposes—especially for PLL generated clock signals. Since only specific ATE platforms have this capability, fabricated electronic circuit products must be placed on a limited and more expensive platform to perform this task. In addition, test time for this jitter testing is large enough to increase test cost and thus decrease overall profit margins for the circuit manufacturer.
Some prior techniques have attempted to resolve this problem by providing “on-chip” test capabilities as a part of the circuit design. However, present on-chip clock jitter test features modify the PLL design by “tapping” signals internal to the PLL circuit (e.g., tapping the “up” and “down” control signals within the PLL circuit per se). Such modifications to PLL circuits create problems for designs using standard cell and component libraries because the standard PLL circuits of the library may not be usable with the jitter test circuits that require “tapping” of signals within the PLL. In other words, the internal signal paths of the PLL library cell may not be exposed in a manner that permits the designer to couple external automated test equipment to the PLL internal signals. Other prior solutions are complex and require additional clock sources that may not be available in the IC design.
Thus, it is an ongoing challenge to thoroughly and cost-effectively test for clock jitter in electronic integrated circuit designs.